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Products: 32-Bit RISC Embedded Processor Cores and Peripheral IP |
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At Avalent Technologies Inc., we design cores with our customers needs in mind. We offer flexible IP licensing, excellent hardware and software support, tools and SoC integration to help our partners meet their fast-paced timetables and individual needs and more quickly bring their product to market.
The heart of our technology is Avalent's 32-Bit RISC Embedded Microprocessor Core. Our processors are designed using a fully static 32-bit architecture, utilizing the latest process technologies from TSMC and UMC.
We offer several varieties of our core to allow customers to pick and choose the core that most fits their needs. Our different architectures range from low-cost, small-die size designs to advanced high-performance designs with DSP functionality and multimedia in mind.
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| | The Janus and Tiber Processor Family |
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- Janus 2CC is optimized for cacheless, low-power operations. The Janus core was designed from the ground up to attain lowest-power draw in its class without sacrificing performance. The Janus 2-CC core has proven software solutions including uClinux, Nucleus OS®, and OSE®.
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- Janus 200 is a Janus family core with an 8k Unified Instruction and Data Cache. Like Janus 2-CC, this core was designed using proprietary low power design techniques that preserve performance. The Janus 200 core has proven software solutions including uClinux, Nucleus OS®, and OSE®.
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- Janus 220 is a 32-bit embedded processor with cache and MMU. The processor was designed utilizing proprietary low power design techniques. The 220 series Janus is capable of running the no-MMU software solutions as well as a variety MMU-based operating systems including Linux and WinCE®.
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- Tiber 1CC is a cacheless, high-performance 32-bit embedded processor with additional DSP instructions. It is ideally suited for applications requiring a cacheless core, a small die size and low-power consumption.
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| | Core Specification Summary: |
| CPU Core |
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Max Clock Frequency |
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Power |
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Cache Size |
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Die Size |
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Technology |
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Description |
| Janus 2CC |
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200MHz |
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< 0.25mw/MHz |
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N/A |
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.9mm2 |
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.18um UMC/TSMC |
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Cacheless, small-footprint, low-cost core with JanusICE |
| Janus 200 |
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200MHz |
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< 0.5mw/MHz |
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8K Unified I/D Cache |
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2.67mm2 |
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.18um UMC/TSMC |
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Low-cost core with cache and JanusICE |
| Janus 220 |
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250MHz |
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< 0.54mw/MHz |
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8K Unified I/D Cache |
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2.76mm2 |
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.18um UMC/TSMC |
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Low-cost core with cache, MMU and JanusICE |
| Tiber 1CC |
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250MHz |
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< 0.25mw/MHz |
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N/A |
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.9mm2 |
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.18um UMC/TSMC |
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Cacheless, advanced, low-cost core with JanusICE |
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| Note: |
| 1. Clock frequency is max frequency using vcc-5% and 125 degree C, worst case process |
| 2. Power is based on fast process conditions, 0 degree C, Vcc (norminal) + 5%. |
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