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Products: The Janus 200 Core |
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Janus 200 Product Synopsis: |
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Janus 200 is a Janus family core with an 8k Unified Instruction and Data Cache. Like Janus 2CC, this core was designed using proprietary low power design techniques that preserve performance. The Janus 200 core has proven software solutions including uClinux, Nucleus OS®, and OSE®. |
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Janus 200 Product Specification: |
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CPU Core |
Clock Frequency |
Power |
Cache Size |
MMU Size |
Die Size |
Technology |
Description |
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Janus Family Core |
200 MHZ |
< 0.5mw/Mhz |
8K Unified I/D Cache |
N/A |
2.67mm2 |
.18um UMC/TSMC |
Low-cost core with cache and JanusICE |
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- Full static design 32-bit RISC processor core
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- 5-stage pipeline for 1 instruction/cycle
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- Fast 32x32 MAC instructions with 3 cycle worst case time
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- 8KB unified power-saving cache
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- Cache lock for critical real-time operations
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- Write-through cache policy, with programmable cacheable and bufferable regions
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- JTAG nonintrusive debug with breakpoints, watchpoints, single step and read/write memory/register capability
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- Fully static flip-flop based design
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- AHB-like bus for high performance
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Core Specification Summary: |
| CPU Core |
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Max Clock Frequency |
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Power |
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Cache Size |
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Die Size |
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Technology |
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Description |
| Janus 2CC |
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200MHz |
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< 0.25mw/MHz |
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N/A |
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.9mm2 |
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.18um UMC/TSMC |
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Cacheless, small-footprint, low-cost core with JanusICE |
| Janus 200 |
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200MHz |
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< 0.5mw/MHz |
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8K Unified I/D Cache |
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2.67mm2 |
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.18um UMC/TSMC |
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Low-cost core with cache and JanusICE |
| Janus 220 |
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200MHz |
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< 0.54mw/MHz |
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8K Unified I/D Cache |
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2.76mm2 |
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.18um UMC/TSMC |
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Low-cost core with cache, MMU and JanusICE |
| Tiber 1CC |
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250MHz |
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< 0.25mw/MHz |
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N/A |
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.9mm2 |
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.18um UMC/TSMC |
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Cacheless, advanced, low-cost core with TiberICE |
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| Note: |
| 1. Clock frequency is max frequency using vcc-5% and 125 degree C, worst case process |
| 2. Power is based on fast process conditions, 0 degree C, Vcc (norminal) + 5%. |
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