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Corporate Info: About Avalent |
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Avalent's founding team of experienced SGI and Intel chip designers had a vision of creating a low-power, high-performance 32-bit RISC processor to fill a niche in the embedded microprocessor market. Starting in 1999, Avalent's engineers have upheld this vision in every milestone that we've achieved.
The net result over the last three years have been two family series of microprocessors: Tiber and Janus. Our first processor, Janus 2CC, was a cacheless 32-bit RISC processor which formed the cornerstone of the Janus Family. Soon after, Janus 200 and 220 addressed the needs of our customers adding cache and MMU functionality.
With each chipset, our vision of providing flexible and superior IP to our customers has slowly become a reality. Ultimately entering 2002, our engineering team has created the Tiber 1CC processor which forms the backbone of our new Tiber Family.
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- In 1999, Avalent Technologies Inc. was formed by a dedicated team of engineers who had extensive experience at building Intel and MIPS processors. The founding team decided to combine their efforts to create an embedded 32-bit RISC microprocessor that was both one of the smallest and lowest-power processors in its class.
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- In 2000, the engineers at Avalent Technologies had achieved the first of many major milestones. Their vision and perseverance culminated in the creation of Avalent's first chipset family. True to their vision, the Janus 2CC chipset rivaled many of the embedded microprocessors in its class and is now the cornerstone of the Janus microprocessor family.
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- In 2001, the Janus 200 chipset series was born. The growing team of Avalent Technologies engineers managed to add a unified data and instruction cache to their first design and still make the design low-power, high-yield and high-performance.
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- In 2001, the Janus 220 chipset was also developed. Featuring both an MMU and a cache block, the Janus 220 chipset rounded out the Janus Family microprocessor set and still adhered to the founding team's initial vision of a small-footprint, low-power processor design.
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- In 2002, Avalent's processor design team came up with a new and improved line of microprocessor. The Tiber 1CC was created with performance, low-power, small-footprint, and high-yield in mind. Tiber is the cornerstone of the Tiber family series processors and with both a cache and MMU and cache system to come in the future.
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In 2003, many ASICs and SOC platforms were developed and distributed to
partners and potential customers. They include, Janus Wireless SOC EV board, Digital Image Processor, Printer Controller Chip,
and Network Processor Chip.
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- In 2004, development and implementation is ongoing for Bluetooth Baseband Controller, Mouse,
Printer Dongle, etc.
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- Fortune Ventures is a multi-national investment firm facilitating investments between Asia and the US. Their strong team of managerially experienced partners help guide our company's visions and technological innovations.
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- Sycamore Ventures is a team of dedicated investment professionals with an aggregate investment experience of more than 45 years. From its offices in Princeton, Silicon Valley and Asia, Sycamore manages more than $550 million in committed capital.
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- For general information about Avalent Technologies, Inc., feel free to email us at info@avalent.com. For information about job opportunities, please see our current openings and email us at jobs@avalent.com. Or send your resume via the fax number noted in the right column.
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- Or you can reach us at our main office in San Jose:
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Avalent Technologies, Inc.
405 River Oaks Parkway
San Jose, CA 95134-2121
Phone: (408) 435-1188
Fax: (408) 435-1511
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